矩形缺陷轮廓的成品率模型

现有成品率及关键面积估计模型中,假定缺陷轮廓为圆,而实际缺陷轮廓为非规则形状.本文提出了矩形缺陷轮廓的成品率模型,该模型与圆模型相比,考虑了缺陷的二维分布特性,接近真实缺陷形状及IC版图布线和成品率估计的特点.比较了新模型与真实缺陷及其圆模型引起的成品率损失,表明新模型在成品率估计方面更加精确,这对成品率精确估计与提高有重要意义.     

IC制造中的真实缺陷轮廓表征方法研究

为了进行有效的集成电路成品率预报及故障分析，与光刻有关的硅片表面缺陷通常被假定为圆形的或方形的，然而，真实缺陷的形貌是多种多样的，本文提出一种准确的缺陷表征模型。该模型考虑了缺陷的真实轮廓，并且针对短路和开路模式，在引起故障概率相同的意义下将起初缺陷等效为缺陷，实现了硅片表面缺陷的精细表征。     

一种有效的IC成品率估算模型

从缺陷造成电路故障的机理出发,给出了芯片故障概率和成品率的计算新模型.利用IC功能成品率仿真系统XD-YES对实际电路XT-1成品率参数的提取,同时利用新模型进行计算,其结果与实际结果符合很好.     

IC缺陷轮廓的分形插值模型

现用于集成电路(IC)成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分形插值的思想直接对真实缺陷的轮廓进行模拟,从而提出了一种新的缺陷轮廓表征模型。实验结果表明:与传统的最大圆模型、最小圆模型及椭圆模型相比,新模型的建模精度有了很大的提高。     

一种有效的IC成品率估算模型

从缺陷造成电路故障的机理出发,给出了芯片故障概率和成品率的计算新模型.利用IC功能成品率仿真系统XD-YES对实际电路XT-1成品率参数的提取,同时利用新模型进行计算,其结果与实际结果符合很好.     

结合版图结构信息的基本门电路故障概率估计

在门级电路可靠性估计方法中,基本门的故障概率P一般采用经验值或人为设定.本文结合基本门的版图结构信息,综合考虑了设计尺寸及缺陷特性等因素,分析了不同缺陷模型下的粒径分布数据,给出了缺陷模型粒径概率密度分布函数的参数c的计算算法,并推导出了P的计算模型.理论分析与在ISCAS85及74系列电路上的实验结果表明,缺陷的分段线性插值模型能较准确地描述电路可靠性模型的低层真实缺陷.对ISCAS85基准电路采用本文方法所得到的电路可靠度与采用美国军用标准MIL-HDBK-217方法所得到的计算结果进行了比较,验证了本文所建P模型的合理性.     

一种IC缺陷轮廓建模的新方法

现用于集成电路（ＩＣ）成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分段线性插值瓣思想直接对真实缺陷的方向尺寸进行逼近,从而提出了一种亲折缺陷轮廓表征模型。实验结果表明：与传统的最大圆模型、最小圆模型及椭圆模型相比,新模型的建模精度有了较大的提高。     

基于制造成品率模型的集成电路早期可靠性估计

缺陷是影响集成电路成品率与可靠性的主要因素.本文在区分缺陷与故障两个概念的基础上,将缺陷区分为成品率缺陷(硬故障)、可靠性缺陷(软故障)和良性缺陷.利用关键区域的面积,给出了一个缺陷成为"硬故障"或"软故障"的概率,给出了精度较高的IC成品率预测模型.利用成品率缺陷与可靠性缺陷之间的关系,给出了工艺线生产的产品的失效率与该工艺线制造成品率之间的定量关系.在工艺线稳定的条件下,通过该工艺线的制造成品率可以利用该关系式可以有效的估计出产品的失效率,可以有效地缩短了新产品的研发周期.     

IC缺陷轮廓的分形插值模型

现用于集成电路（ＩＣ）成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分形插值的思想直接对真实缺陷的轮廓进行模拟,从而提出了一种新的缺陷轮廓表征模型。实验结果表明：与传统的最大圆模型,最小圆模型及椭圆模型相比,新模型的建模精度有很大的提高。     

VLSI成品率统计中的缺陷成团效应及统计参数与面积的关系

本文以负二项分布为基础,在对两个实测统计结果进行分析的基础上,给出了VLSI成品率与缺陷分布统计中有关成团因子与芯片面积关系的模型.在模型的推导中考虑了由于缺陷的成团聚集效应引起的区域之间缺陷分布的相关性这一内在因素.模型与本文给出的两个实测统计结果的一致性很好.     

Yield Modeling of Rectangular Defect Outline

In integrated circuits,the defects associated with photolithography are assumed to be in the shape of circular discs in order to perform the estimation of yield and fault analysis.However,real defects exhibit a great variety of shapes.In this paper,a novel yield model is presented and the critical area model of short circuit is correspondingly provided.In comparison with the circular model corrently available,the new model takes the similarity shape to an original defect,the two-dimensional distributional characteristic of defects,the feature of a layout routing and the character of yield estimation into account.As for the aspect of prediction of yield,the experimental results show that the new model may predict the yield caused by real defects more accurately than the circular model does.It is significant that the yield is accurately estimated and improved using the proposed model.     

IC缺陷轮廓分形维估计的小波方法

为了有效的进行集成电路成品率预报和故障分析,与光刻有关的硅片表面缺陷通常被假定为圆形、椭圆或方形.然而,真实缺陷的形貌是多种多样的,它们的形状对集成电路的成品率估计有重要影响.本文讨论了缺陷轮廓所具有的分形特征,并用小波变换的方法对其分形维数进行了估计,估计结果与实例的特征相符,从而为缺陷轮廓的表征和计算机模拟提供了新的特征参数.     

考虑缺陷形状分布的IC成品率模型

实现了基于圆缺陷模型的蒙特卡洛关键面积及成品率估计,模拟了圆缺陷模型估计的成品率误差与缺陷的矩形度之间的关系,提出了更具有一般性的两种集成电路成品率模型,它们分别对应于矩形度相同和不同的缺陷．仿真结果表明该模型为成品率的精确表征提供了新途径．     

Equivalent circular defect model of real defect outlines in the ICmanufacturing process

For efficient yield prediction and inductive fault analysis of integrated circuits (IC's), it is usually assumed that defects related to photolithography have the shape of circular discs or squares. Real defects, however, exhibit a great variety of shapes. This paper presents an accurate model to characterize those real defects. The defect outline is used in this model to determine an equivalent circular defect such that the probability that the circular defect causes a fault is the same as the probability that the real defect causes a fault, so a norm is available which ran be used to determine the accuracy of a defect model, and thus estimate approximately the error that will be aroused in the prediction of fault probability of a pattern by using circular defect model. Finally, the new model is illustrated with the real defect outlines obtained by optical inspection     

Modeling of real defect outlines and parameter extraction using acheckerboard test structure to localize defects

For efficient yield prediction and inductive fault analysis, it is usually assumed that defects have the shape of circular discs or squares. Real defects, however, exhibit a great variety of different shapes. This paper presents a more accurate model. The defect outline is approximated by an ellipse, and an equivalent circular defect is determined that causes a fault with the same probability as the real defect. To utilize this model, only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a novel test structure design. The checkerboard test structure uses the boundary pad frame of standard chips and thus achieves a large defect sensitive area. This area is partitioned into many small regions that can be analyzed separately. Defects are localized by simple electrical measurements. This allows an efficient optical inspection that can provide detailed information about the detected defects     

Defect Simulation Methodology for iDDT Testing

The International Technology Roadmap for Semiconductors (ITRS) identifies two main challenges associated with the testing of manufactured ICs. First, the increase in complexity of semiconductor manufacturing process, physical properties of new materials, and the constraints imposed by resolution of lithography techniques etc., give rise to more complex failure mechanisms and hard-to-model defects that can no longer be abstracted using traditional fault models. Majority of defects, in today's technology, include resistive bridging and open defects with diverse electrical characteristics. Consequently, conventional fault models, and tools based on these models are becoming inadequate in addressing defects resulting from new failure mechanisms. Second, the defect detection resolution of main-stream I_DDQ testing is challenged by significant elevation in off-state quiescent current and process variability in newer technologies. Overcoming these challenges demands innovative test solutions that are based on realistic fault models capable of targeting real defects and thus, providing high defect coverage. In prior works power supply transient current or i_DDT testing has been shown to detect resistive bridging and open defects. The ability of transient currents to detect resistive opens and their insensitivity (virtually) to increase in static leakage current make i_DDT testing all the more attractive. However, in order to integrate i_DDT based methods into production test flows, it is necessary to develop a fault simulation strategy to assess the defect detection capability of test patterns and facilitate the ATPG process. The analog nature of the test observable, i.e., i_DDT signals, entail compute intensive transient simulations that are prohibitive. In this work, we propose a practical fault simulation model that partitions the task of simulating the DUT (device under test) into linear and non-linear components, comprising of power/ground-grid and core-logic, respectively. Using divide-and-conquer strategy, this model replaces the transient simulations of power/ground-grid with simple convolution operations utilizing its impulse response characteristics. We propose a path isolation strategy for core-logic as a means of reducing the computational complexity involved in deriving i_DDT signals in the non-linear portion. The methodology based on impulse response functions and isolated path simulation, can enable i_DDT fault simulation without having to simulate the entire DUT. To our knowledge, no practical technique exists to perform fault simulation for i_DDT based methods. The proposed fault simulation model offers two main advantages, first, it allows fault induction at geometric or layout level, thus providing a realistic representation of physical defects, and second, the current/voltage profile of power/ground-grid, derived for i_DDT fault simulation, can be used to perform accurate timing verification of logic circuit, thus facilitating design verification. In summary, the proposed fault simulation framework not only enables the assessment of defect detection capabilities of i_DDT test methodologies, but also establishes a platform for performing defect-based testing on practical designs.     

IC缺陷轮廓多分形特征研究

IC真实缺陷轮廓曲线的形状特征对集成电路成品率预报及故障分析有重要影响。该文提出缺陷轮廓曲线具有多分形特征,以某一真实缺陷为例,用小波变换模极大(WTMM)的方法估计了其轮廓曲线参数方程的多分形谱,该结果为硅片表面缺陷的精细表征及其计算机模拟作了有益探索。     

基于深度学习的航拍电网绝缘子缺陷检测

电网绝缘检测缺陷的准确检测是电网运行状态有效监测及故障诊断前提,基于无人机航拍电网绝缘子图像,为解决深度学习缺陷检测存在的误检测和局部信息丢失问题,提出基于改进深度学习全卷积网络的缺陷自动检测算法,算法通过改进FCN的VGG结构、扩展滤波器尺寸、取消全连接层Dropout及模型深度,实现FCN模型在绝缘子缺陷检测方面的有效改进,实验结果表示,改进模型在较少运行时间增加基础上,有效提高了对绝缘子缺陷检测的性能和对背影的鲁棒性,取得了比已有算法更有优势的检测结果。