不同阳极结构二维PSD的电流—位置输出特性

本文介绍了四边形电极结构,四边形电极改进结构和带电阻边框的方框形电极结构3种二维位敏器件（PSD）的结构和工作原理,导出了3种结构PSD的输出电流理论表达式和位置线性度网络图。结果表明：四边形电极结构PSD的位置偏差最大,中央60％光敏区域内最大位置误差约10．0％,与实验结果相符;四边形电极改进结构PSD在中央60％光敏区域内最大位置误差约5．0％;带电阻边框的方框形电极结构,当边框电阻很小时,位置信号与输出电流之间满足线性关系,实验测得中央79％光敏区域内的均方根位置误差小于0．3％。     

负载电阻及光敏层电阻率对一维PSD的影响

分析了光敏层电阻率的非均匀分布及负载电阻不为零情况下对一维位置敏感探测器(PSD)位置误差的影响。分析结果表明,光敏层电阻率的非均匀分布对一维PSD的边缘位置误差影响很小,而负载电阻则是影响边缘误差的主要因素。减小负载电阻能够减小PSD的边缘误差。     

Ar离子注入边缘终端准垂直GaN肖特基势垒二极管

为了研究离子注入边缘终端对准垂直GaN肖特基势垒二极管性能的影响,对器件进行了二维模拟仿真,分析了终端区域尺寸对肖特基结边缘处峰值电场及正向特性的影响,得到了宽度5μm、厚度200 nm的最优终端区域尺寸.基于工艺仿真软件设计了Ar离子注入工艺参数,依次以30keV、5.0×1013 cm-2,60 keV、1.5×1014cm-2和 140 keV、4.5×1014cm-2的注入能量和注入剂量进行多次注入,形成了Ar离子终端结构.采用Ar离子注入终端的GaN二极管的反向击穿电压从73 V提高到146 V,同时注入前后器件正向特性变化不大.结果表明,采用优化尺寸参数的终端结构能够有效降低肖特基结边缘处的峰值电场强度,从而提高器件的反向击穿电压.     

一种基于光学传感器的新型触摸板的设计

针对现有各种交互式触摸板系统在性能及成本上的不足,设计了一种基于光学敏感器件PSD的触摸板,采用了由反射镜等光学器件构成的简单光学系统,将触摸笔笔尖的红外光源发出的光成像于光敏器件PSD上,从而确定触摸点的位置坐标.光敏器件PSD的使用,使系统具有很高的数据处理速度,且设计结构简单紧凑易于集成、成本低、性能优越,适用于...     

四边形电极结构PSD的特性测试与分析

根据单面分流四边形电极结构的正方形PSD的原理 ,测试并分析我们研制的 3mm×3mm正方形PSD的性能。给出反偏电压、光谱响应、暗电流、极间电容、极间阻抗、位置分辨率和位置线性特性等性能的测试结果。并在分析位置特性的非线性失真机理的基础上 ,给出位置特性非线性失真的修正方法。     

位置敏感探测器的响应时间分析

位置敏感探测器(PSD)的响应时间直接影响其动态探测入射光位置的准确性.分析了电势堆积现象,以四边形二维PSD为例,建立了PSD响应时间的仿真模型,分析了对响应时间的影响因素.结果表明,PSD响应时间随着光敏面大小、p型层电阻值以及级间电容的增大而同比例增大;在PSD器件的结构参数和物性参数不变的情况下,光源入射能量与器件的响应时间无关.     

氮离子注入后拟南芥种子表皮的扫描电镜观察

应用扫描电镜观察了低能N^ 注入拟南芥干种子后表层细胞结构的变化。结果表明,拟南芥种子的N^ 离子注入区域与未注入区域相比,离子注入区在一定程度上发生变化并伴随有表层细胞的损伤。随着离子剂量的增大,离子对种子细胞的损伤程度增大,且种子表面有裂痕生成。另外,经注入种子的表面分布有许多散在的固体颗粒状物质,其密集程度也随离子剂量的增加而增大。     

改善位置敏感器信噪比的信号处理系统

PSD(Position Sensitive Detector)位置敏感探测器,是一种能将人射光点位置转换为电流信号的半导体光电检测元件,作为半导体光敏探测器,其固有的缺陷就是受温度和背景光影响较大.采用可编程逻辑器件电路可以较好地减小这种影响,而且减少了传统的PSD信号处理电路中模拟器件噪声,通过仿真测试证明,噪声有效降低、改善了器件的信噪比,有利于精确测量.     

四边形结构PSD的输出特性研究

对四边形结构二维位置敏感探测器(PSD)的单方向输出特性进行了实验研究，并用有限元法(FEM)进行了模拟和计算，计算结果与实验结果完全吻合。作为比较，还模拟计算了正方形一维PSD的输出特性。     

阶梯栅氧结构的NLDMOS热载流子效应研究

本文对一种新型的阶梯栅氧结构的NLDMOS（Step Gate Oxide NLDMOS , SG-NLDMOS）的热载流子效应进行了研究。采用直流电压应力实验、TCAD仿真、电荷泵测试等方法,对退化现象进行了分析,并提出了退化机制。然后研究了漂移区注入剂量对器件热载流子效应的影响,结果表明低的漂移区注入剂量可以更有效地减小器件导通电阻的退化。     

位置敏感探测器光斑脱靶误差补偿方法研究

为了提高位置敏感探测器(PSD)的位置检测范围,解决光斑在探测器光敏面脱靶时无法准确定位光斑的问题,提出一种光斑脱靶误差补偿方法,分析了脱靶前后PSD检测光斑能量重心变化规律,建立了PSD光强信号与位置检测误差间的函数关系。实验结果表明:当PSD光敏面尺寸为12mm×12mm时,对于半径为5mm的高斯光斑,通过所提出的光斑补偿方案补偿后PSD的X轴检测范围提高了66.7%,位置检测平均相对误差不超过5%,该方法对提高PSD位置检测性能具有重要的意义。     

ATP跟瞄系统中位置敏感探测器测量精度研究

为满足星－地量子通信中 ATP 跟瞄系统对二维位置敏感探测器（PSD）的精密性、实时性、可靠性的要求,基于 LabVIEW 设计了 PSD 精度测量与误差修正系统。首先,采用驱动平台带动激光光源,通过扫描 PSD 光敏面,获得电压值并计算出光斑位置,分析非线性成因,采用多项式拟合法建立实际值与测量值间的数学模型,得到非线性修正函数。然后,结合光学三角测量对被测物体进行微位移和角度测量,并对测量结果进行误差修正。实验结果表明,经过修正后 PSD 位置误差显著减小,满足系统对 PSD 的需求,通过 LabVIEW 软件编程提高了系统的测试效率。     

An asymmetrically doped buried-layer (ADB) structure forlow-voltage mixed analog-digital CMOS LSI's

A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration “pocket” layer near the channel edge of the buried layer only on the source side and a low-impurity surface region through the channel. The source-side channel region determines the threshold voltage and the drain-side channel region absorbs the drain potential. The low-impurity surface region reduces impurity scattering and enables high transconductance. The fabricated ADB CMOS structure increased the drain output resistance, transconductance, and saturation current down to a 0.3-μm channel length, as compared to a control structure. Furthermore, the drain junction capacitance was reduced because of the low impurity concentration beneath the drain region     

Origin of low-frequency noise in pentacene field-effect transistors

Measurements of power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors reveal the preponderance of a 1/f-type PSD behavior with the amplitude varying as the squared transistor gain and increasing as the inverse of the gate surface area. Such features impose an interpretation of LFN by carrier number fluctuations model involving capture/release of charges on traps uniformly distributed over the gate surface. The surface slow trap density extracted by the noise analysis is close to the surface states density deduced independently from static I(V) data, which confirms the validity of the proposed LFN interpretation. Further, we found that the trap densities in bottom-contact (BC) devices were higher than in their top-contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in the contact regions in particular. At the highest bias the noise originating from the contact resistance is also shown to be a dominant component in the PSD, and it is well explained by the noise originating from a gate-voltage dependent contact resistance. A gate area scaling was also performed, and the good scaling and the dispersion at the highest bias confirm the validity of the applied carrier number fluctuations model and the predominant contact noise at high current intensities.     

瞬态光响应法测试中波碲镉汞器件少子寿命的新方法

在测试中波碲镉汞光伏器件的瞬态响应时,当激光光斑照射器件表面位置距离光敏面较远时,器件表现为特殊的双峰脉冲响应现象,分析表明出现这种异常双脉冲现象的原因是光敏区内的少子漂移和光敏区外侧向收集的少子扩散有时间上的差异。通过对器件施加反向偏压,脉冲响应随反向偏压的增大由双峰变成单峰的实验结果,验证了少子侧向收集是导致器件形成双峰的主要原因。对第二个峰拟合得到p区的少数载流子寿命。将瞬态响应获得的少子寿命与该p型中波碲镉汞材料的理论计算和光电导衰退法得到的少子寿命相对比,发现三种方式得到的少子寿命随温度的变化趋势基本一致,这说明了可以通过瞬态光响应得到中波碲镉汞器件的少子寿命。     

基于PSD的路面粗糙度快速检测方法研究

针对我国目前路面粗糙度仍然采用铺砂法和摆式仪手工检测的落后现状,提出了基于光电位置传感器(PSD)的路面粗糙度快速检测新方法.依据铺砂法的检测原理,给出了基于PSD的路面粗糙度快速检测的数学模型和硬件设计原理及标定结果.实验证明,该检测方法可有效地提高检测速度和检测精度.     

Planar InP avalanche photodiode with Zn-diffused guard ring

A guard ring structure with a p+-n?-n junction formed by Zn diffusion at 450°C gave a high gain planar InP avalanche photodiode. A maximum multiplication factor of more than 50 was obtained uniformly within the photosensitive area without edge breakdown.     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices