| 对数/指数算法的改进及其VLSI实现 |
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| 引用本文： | 赵海燕,周晓方,周电.对数/指数算法的改进及其VLSI实现[J].计算机工程与应用,2007,43(7):104-107. |
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| 作者姓名： | 赵海燕 周晓方 周电 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海201203 |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | 提出了一种二进制数的指数/对数运算的线性近似的改进算法,并VLSI实现。该算法能较好地提高精度,相比于现有最新文献提出的算法,对数运算的相对误差减少了46.1%,指数运算的相对误差减少了32.2%。实现时,设计了前导1探测电路和减小误差的误差补偿电路。该算法VLSI实现简单,只需组合逻辑就能在一个时钟周期内得到计算结果。
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| 关 键 词： | 对数/指数运算 线性近似 硬件实现 |
| 文章编号： | 1002-8331（2007）07-0104-04 |
| 修稿时间： | 2006-11 |
Arithmetic research of logarithm and anti-logarithm converters and VLSI implementation |
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| ZHAO Hai-yan,ZHOU Xiao-fang,ZHOU Dian.Arithmetic research of logarithm and anti-logarithm converters and VLSI implementation[J].Computer Engineering and Applications,2007,43(7):104-107. |
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| Authors: | ZHAO Hai-yan ZHOU Xiao-fang ZHOU Dian |
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| Abstract: | This paper presents an improved binary-to-binary logarithm and anti-logarithm line approximation including its VLSI implementation.This arithmetic can increase precision well,compared with the newest references,the logarithm converter's percent error reduces 46.1% and the anti-logarithm converter's percent error reduces 32.2%.A leading-one detector circuit is designed to obtain the leading-one position of an input binary word and error-correcting circuit is designed to reduce error.The implementation is simply,uses combinational logic only and calculates the approximation in a single clock cycle. |
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| Keywords: | logarithm/anti-logarithm converter line approximation VLSI implementation |
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