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碲镉汞e-APD 焦平面数字化读出电路设计
引用本文:陈国强,张君玲,王攀,周杰,高磊,丁瑞军.碲镉汞e-APD 焦平面数字化读出电路设计[J].红外与激光工程,2014,43(9):2798-2804.
作者姓名:陈国强  张君玲  王攀  周杰  高磊  丁瑞军
作者单位:1.中国科学院上海技术物理研究所中国科学院红外成像材料与器件重点实验室,上海200083;
摘    要:HgCdTe e-APD 工作于线性模式,通过内雪崩倍增效应将一个微弱的信号放大多个数量级。介绍了一个具有列共用ADC 制冷型(77 K)数字化混成式HgCdTe e-APD FPA 读出电路,可以应用于门控3D-LARDAR 成像,有主被动双模式成像功能。Sigma-delta 转换器比较适合于中规模128128 焦平面列共用ADC。调制器采用2-1 MASH 单比特结构,开关电容电路实现,数字抽取滤波器采用CIC 级联梳状滤波器。采用GLOBALFOUNDRIES 0.35 m CMOS 工艺,中心距100 m。设计了量化噪声抵消逻辑消除第一级调制器量化噪声,采用数字电路实现。CIC 抽取滤波器的每一级寄存器长度以方差为指标截尾,以降低硬件消耗。并且数字抽取滤波器工作电压降低到1.5 V,可以进一步降低功耗。仿真显示sigma-delta 转换器精度大于13 bit,功耗小于2.4mW,转换速率7.7 k Samples/s。

关 键 词:碲镉汞e-APD    读出电路    主被动双模式成像    sigma-delta  ADC    制冷型红外焦平面
收稿时间:2014-01-05

Design of digital ROIC for HgCdTe e-APD FPA
Affiliation:1.Key Laboratory of Infrared Imaging Materials and Detectors,Shanghai Institute of Technical Physics,Chinese Academy of Sciences,Shanghai 200083,China;2.University of Chinese Academy of Sciences,Beijing 100049,China
Abstract:HgCdTe electron injection avalanche photodiodes(e-APDs) work in linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism. The design of digital ROIC with a column-shared ADC for cooled (77 K) hybrid e-APDs FPA was presented in this paper. Sigma-delta conversion was a promising solution for high-performance and medium size FPA as 128 128. A multistage noise shaping (MASH) 2 -1 single bit architecture sigma-delta ADC with switched-capacitor circuits was designed for column-shared ADC. A cascaded integrator-comb (CIC) filter was designed as the digital decimator filter. The circuit was implemented in the GLOBALFOUNDRIES 0.35 m CMOS process on the basis of a 100 m pixel pitch. A quantization noise subtraction circuit in modulator was designed to subtract the quantization noise of first-stage modulator. The register word length of the filter in each stage was carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5 V. Simulation results showed that the sigma-delta conversion achieved the resolution higher than 13 bits and 2.4 mW power consumption per ADC at 7.7 k Samples/s rate.
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